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24C08B/16B
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Symbol
F CLK
T HIGH
T LOW
T R
T F
T HD : STA
Min
—
4000
4700
—
—
4000
Max
100
—
—
1000
300
—
Units
kHz
ns
ns
ns
ns
ns
Remarks
(Note1)
(Note 1)
After this period the first clock
pulse is generated
START condition setup
T SU : STA
4700
—
ns
Only relevant for repeated
time
START condition
Data input hold time
Data input setup time
STOP condition setup time
T HD : DAT
T SU : DAT
T SU : STO
0
250
4000
—
—
—
ns
ns
ns
Output valid from clock
Bus free time
T AA
T BUF
—
4700
3500
—
ns
ns
(Note 2)
Time the bus must be free before
a new transmission can start
Output fall time from V IH
T OF
—
250
ns
(Note 1), C B ≤ 100 pF
min to V IL max
Input filter spike suppres-
T SP
—
50
ns
(Note 3)
sion (SDA and SCL pins)
Write cycle time
Endurance
T WR
—
—
1M
10
—
ms
cycles
Byte or Page mode
25°C, V CC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. C B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T SP and V HYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T I specification.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
SCL
T F
T LOW
T HIGH
T R
SDA
IN
T SU : STA
T SP
T HD : STA
T HD : DAT
T SU : DAT
T SU : STO
T AA
T HD : STA
T AA
T BUF
SDA
OUT
? 2004 Microchip Technology Inc.
DS21081G-page 3
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